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DS1044
DS1044 4-in-1 High-Speed Silicon Delay Line
FEATURES
PIN ASSIGNMENT
IN1 NC IN2 IN3 IN4 NC GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC NC OUT1 NC OUT2 OUT3 OUT4
* All-silicon timing circuit * Four independent buffered delays * Initial delay tolerance 1.5 ns * Stable and precise over temperature and voltage * Leading
and trailing edge precision preserves the input symmetry
* Standard 14-pin DIP, 14-pin SOIC (150 mil) * Vapor phase, IR and wave solderable * Available in Tape and Reel
DS1044 14-PIN DIP DS1044R 14-PIN SOIC (150 MIL) See Mech. Drawings Section
PIN DESCRIPTION
IN1-IN4 OUT1-OUT4 NC VCC GND - - - - - Input Signals Output Signals No Connection +5 Volt Supply Ground
DESCRIPTION
The DS1044 series is a 4-in-1 version of the low- power, +5 Volt, high speed, DS1035. The DS1044 series of delay lines have four independent logic buffered delays in a single package. The device is Dallas Semiconductor's fastest 4-in-1 delay line. It is available in a standard 14-pin DIP and 14-pin SOIC. The device features precise leading and trailing edge accuracies. It has the inherent reliability of an all-silicon delay line solution. The DS1044's nominal tolerance is 1.5 ns and an additional tolerance over temperature and voltage of 1.0 ns for the faster delays. Each output is capable of driving up to 10 LS loads. Standard delay values are indicated in Table 1. Customers may contact Dallas Semiconductor at (972) 371-4348 for further information.
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DS1044
LOGIC DIAGRAM Figure 1
IN OUT
TIME DELAY
ONE OF FOUR
PART NUMBER DELAY TABLE (tPLH, tPHL) Table 1
PART NUMBER DS1044-5 DS1044-6 DS1044-7 DS1044-8 DS1044-10 DS1044-12 DS1044-14 DS1044-18 DS1044-20 DS1044-25 DELAY PER OUTPUT (ns) 5 6 7 8 10 12 14 18 20 25 INITIAL TOLERANCE 1.5 ns 1.5 ns 1.5 ns 1.5 ns 1.5 ns 1.5 ns 1.5 ns 1.5 ns 1.5 ns 2.0 ns TOLERANCE OVER (temp and voltage) 1.0 ns 1.0 ns 1.0 ns 1.0 ns 1.0 ns 1.0 ns 1.5 ns 1.5 ns 1.5 ns 1.5 ns
NOTES:
1. Nominal conditions are +25C and VCC=+5.0 volts. 2. Temperature range of 0C to 70C and voltage range of 4.75 volts to 5.25 volts. 3. Delay accuracy are for both leading and trailing edges.
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DS1044
TEST SETUP DESCRIPTION
Figure 2 illustrates the hardware configuration used for measuring the timing parameters of the DS1044. The input waveform is produced by a precision pulse generator under software control. Time delays are measured by a time interval counter (20 ps resolution) connected
to the output. The DS1044 output taps are selected and connected to the interval counter by a VHF switch control unit. All measurements are fully automated with each instrument controlled by the computer over an IEEE 488 bus.
DS1044 TEST CIRCUIT Figure 2
PULSE GENERATOR
START
TIME INTERVAL COUNTER 50
4
INPUTS
STOP
UNIT UNDER TEST
VHF SWITCH CONTROL UNIT
OUT 50
OUTPUTS 1-4
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DS1044
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature Short Circuit Output Current -1.0V to +7.0V 0C to 70C -55C to +125C 260C for 10 seconds 50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
PARAMETER Supply Voltage Active Current High Level Input Voltage Low Level Input Voltage Input Leakage High Level Output Current Low Level Output Current SYMBOL VCC ICC VIH VIL IL IOH IOL 0V(0C to 70C; VCC=+5V 5%)
TYP 5.00 MAX 5.25 45 VCC+0.5 0.8 1.0 -1.0 UNITS V mA V V A mA mA
AC ELECTRICAL CHARACTERISTICS
PARAMETER Period Input Pulse Width Input-to-Tap Output Delay Output Rise or Fall Time Power-up Time SYMBOL tPERIOD tWI tPLH, tPHL tOR, tOF tPU MIN 2 (tWI) 100% of Tap Delay Table 1 2.0 2.5 100 TYP MAX
(+25C; VCC=5V 5%)
UNITS ns ns ns ns ms NOTES 3 3
CAPACITANCE
PARAMETER Input Capacitance SYMBOL CIN MIN TYP MAX 10 UNITS pF
(tA=25C)
NOTES
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DS1044
TEST CONDITIONS
Ambient Temperature: 25C 3C Supply Voltage (VCC): 5.0V 0.1V Input Pulse: High: 3.0V 0.1V Low: 0.0V 0.1V Source Impedance: 50 Max. Rise and Fall Time: 3.0 ns Max. - Measured between 0.6V and 2.4V. Pulse Width: 500 ns Pulse Period: 1 s Output Load Capacitance: 15 pF Output: Each output is loaded with the equivalent of one 74F04 input gate. Data is measured at the 1.5V level on the rising and falling edges. Note: The above conditions are for test only and do not restrict the devices under other data sheet conditions.
TIMING DIAGRAM
PERIOD tRISE tFALL
80% 1.5V 20% IN tWI tPHL tPLH tWI 1.5V 1.5V
1.5V OUT
1.5V
NOTES:
1. All voltages are referenced to ground. 2. @ VCC=5 volts and 25C, delay accuracy on both the rising and falling edges within tolerances given in Table 1. 3. Pulse width and duty cycle specifications may be exceeded, however, accuracy will be application sensitive with respect to de-coupling, layout, etc.
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DS1044
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. tWI (Pulse Width): The elapsed time on the pulse between the 1.5 volt point on the leading edge and the 1.5 volt point on the trailing edge or the 1.5 volt point on the trailing edge and the 1.5 volt point on the leading edge. tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge on the input pulse. tPLH (Time Delay, Rising): The elapsed time between the 1.5 volt point on the leading edge of the input pulse and the 1.5 volt point on the leading edge of the output pulse. tPHL (Time Delay, Falling): The elapsed time between the 1.5 volt point on the falling edge of the input pulse and the 1.5 volt point on the falling edge of the output pulse.
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